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Espressif Systems /ESP32-C6 /EXTMEM /L1_ICACHE_CTRL

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Interpret as L1_ICACHE_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE_SHUT_IBUS0)L1_ICACHE_SHUT_IBUS0 0 (L1_ICACHE_SHUT_IBUS1)L1_ICACHE_SHUT_IBUS1 0 (L1_ICACHE_SHUT_IBUS2)L1_ICACHE_SHUT_IBUS2 0 (L1_ICACHE_SHUT_IBUS3)L1_ICACHE_SHUT_IBUS3 0L1_ICACHE_UNDEF_OP

Description

L1 instruction Cache(L1-ICache) control register

Fields

L1_ICACHE_SHUT_IBUS0

The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
L1_ICACHE_SHUT_IBUS1

The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
L1_ICACHE_SHUT_IBUS2

Reserved
L1_ICACHE_SHUT_IBUS3

Reserved
L1_ICACHE_UNDEF_OP

Reserved

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data